Intel Details Next

Intel has further detailed its next-gen Xeon Data Center CPU lineup for 2024 which will include Granite Rapids & Sierra Forest.

The HotChips 2023 session kicked off with Intel explaining how the modern data center needs are expanding and becoming more and more workload-centric. You can have a wide variety of HPC, AI, compute-intensive, High-Density, & general-purpose workloads which means that a single type of core isn't always the best choice to do all sorts of these works. As such, Intel has already committed to offer its own answer to AMD's Zen 4 and Zen 4C strategy and that comes with P-Core and E-Core specific Xeon CPUs.

The P-Core Xeon CPUs are branded under the Granite Rapids family which are optimized around compute-intensive and AI workloads while the E-Core Xeon CPUs are branded under the Sierra Forest family & these are optimized for Efficiency in high-density and scale-out workloads. Both CPU families share a common platform foundation and shared software stack which means that they are both compatible with each other on the same platforms.

Diving into the modularity aspects of its next-gen SoC architecture, Intel details how its Xeon CPUs, especially Granite Rapids, will feature separate compute and IO silicon chiplets. These chiplets will be interconnected using the EmiB fabric on the same package, offering high bandwidth and low latency path lanes.

Talking about platform, the Intel Granite Rapids-SP Xeon CPUs will scale across 1S and up to 8S platforms while Sierra Forest chips will scale across 1S and up to 2S solutions. Both CPUs will feature a range of SKUs with variable core counts and thermal targets. The next-gen Xeon CPU platform will also support up to 12-channel DDR/MCR (1-2DPC) memory, up to 136 PCIe Gen 5 lanes with 6 UPI links (CXL 2.0).

Some SKUs shown as renders give us a look at three possible configurations which include a single compute die with two IO chiplets, a dual Compute Chiplet & dual IO chiplet configuration, and lastly the top triple Compute Chiplet and dual IO chiplet configuration.

Intel will be using a modular mesh fabric to access all the chiplets which enables:

The Compute die on the Intel Xeon Granite Rapids chips will aim for higher performance & efficiency by utilizing the latest Intel 3 process node and also enable a flexible row/column structure. The Core Tile itself will consist of the CPU cores which are based on the Redwood Cove architecture and L2 cache, LLC+SF+CHA slice, and the mesh fabric interface.

The Core Tile can be adapted to both P-Cores and E-Cores. Plus, there's the Advanced Memory subsystem on the same die which features a common controller/IO and full support for CXL-attached memory.

For Sierra Forest, the Intel E-Core Xeon family, the CPU's core tile will offer 2-4 cores per module which will utilize a shared L2 cache, a shared frequency/voltage domain, and a shared mesh fabric interface. Each core is single threaded so that gives us 144 cores and 144 threads in the top SKU's Compute Tile packaged within 36 core tiles. The LLC slice is shared amongst all cores in a socket and offers a high bandwidth pipeline. So that gives us up to 144 MB of L2 cache and 108 MB of LLC.

Based on the current roadmap, Intel's 5th Gen Emerald Rapids Xeon CPUs will be launching in Q4 of 2023 followed by Sierra Forest in the first half of 2024 and these will soon be followed by the P-Core powered Granite Rapids family.